1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems which support predication instructions and which include multiple instruction pipelines.
2. Description of the Prior Art
It is known to provide data processing systems with multiple instruction pipelines such that instructions may be decoded and executed in the different instruction pipelines at the same time thereby increasing the speed of operation by increasing the overall instruction throughput. Such data processing systems are sometimes referred to as superscalar or multiple issue data processing systems.
It is also known to provide data processing systems which support predication instructions. One example of a predication instruction is the IT instruction of the Thumb-2 instruction set of the processors designed by ARM Limited Cambridge England. The IT predication instruction acts to render between one and four following unconditional program instructions to act as conditional program instructions which either are executed or are not executed in dependence upon condition codes specified in the IT instruction. This type of instruction is useful, for example, in an instruction set which does not provide condition codes for all instructions as a way of improving code density and as a way of providing condition code behaviour for certain sequences of instructions.
A particular problem arises with predication instructions in the context of processors having more than one instruction pipeline. When a predication instruction is being decoded in one instruction pipeline there may be another instruction being decoded in parallel in another instruction pipeline which is to be predicated by that predication instruction. However, the predication instruction will not be decoded and recognised until it has progressed a certain distance along its instruction pipeline and so it will not be known whether or not the instruction following in the sequence of program instructions but being processed in parallel with the predication instruction is or is not to be predicated until it has also progressed at least the same certain distance along its instruction pipeline. The way in which the instruction which may or may not be predicated is decoded is already dependent upon whether or not it is predicated at an early stage in its progress along the instruction pipeline, and the detection result of a predication instruction within its pipeline is not available sufficiently early to control this. It is undesirable to slow the instruction pipelines to a degree that would allow a predication instruction in one pipeline to be decoded and recognised as well as supplying a such recognition signal to another pipeline in sufficient time that the decoding in that other pipeline could also be completed within the required early decoding stage.